1. Field of the Invention
The present invention relates in general to data output buffer circuits used in semiconductor integrated circuits, and more particularly to a data output buffer circuit for a semiconductor device in which a single data line precharged with a half voltage (Vcc/2) is used to enhance the operation speed and reduce a layout area on the chip.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram of a conventional data output buffer circuit for a semiconductor device employing a single data line for the data transfer. As shown in this drawing, the conventional data output buffer circuit comprises a NAND gate G1 for inputting a read data signal r.sub.- data on a read data line and a data output buffer enable signal oe, an inverter G2 for inverting the data output buffer enable signal oe, a NOR gate G3 for inputting the read data signal r.sub.- data and an output signal from the inverter G2, a PMOS pull-up transistor Q1 connected between a supply voltage source Vdd and a node N3, an NMOS pull-down transistor Q2 connected between the node N3 and a ground voltage source Vss, and an output terminal dout connected to the node N3. The PMOS pull-up transistor Q1 has its gate connected to an output terminal of the NAND gate G1 and the NMOS pull-down transistor Q2 has its gate connected to an output terminal of the NOR gate G3.
The operation of the conventional data output buffer circuit with the above-mentioned construction will hereinafter be described.
When the read data signal r.sub.- data is placed on the read data line, it is logically combined with the data output buffer enable signal oe by the NAND gate G1 and NOR gate G3 and then applied to the gates of the PMOS pull-up transistor Q1 and NMOS pull-down transistor Q2. At this time, if the read data signal r.sub.- data is high in logic, signals on nodes N1 and N2 are both low in logic, thereby, causing the PMOS pull-up transistor Q1 to be turned on and the NMOS pull-down transistor Q2 to be turned off. As a result, the read data signal r.sub.- data of high logic is transferred to the output terminal dout. On the contrary, in the case where the read data signal r.sub.- data is low in logic, the signals at the nodes N1 and N2 are both high in logic, thereby causing the PMOS pull-up transistor Q1 to be turned off and the NMOS pull-down transistor Q2 to be turned on. As a result, the read data signal r.sub.- data of low logic is transferred to the output terminal dout.
The above-mentioned conventional data output buffer circuit is advantageous in that it occupies a small area on the chip because of the use of single data line. However, error data may be outputted in the case where the data output buffer enable signal oe is enabled earlier than the read data signal r.sub.- data. For this reason, the data output buffer enable signal oe must be enabled later than the read data signal r.sub.- data. This results in a reduction in operation speed of the data output buffer circuit.
Referring to FIG. 2, there is shown a circuit diagram of a conventional data output buffer circuit for a semiconductor device employing two data lines for the data transfer. As shown in this drawing, the conventional data output buffer circuit comprises a NAND gate G4 for inputting a first read data signal rd on a first read data line and a data output buffer enable singal oe, a NAND gate G5 for inputting a second read data signal /rd on a second read data line and the data output buffer enable signal oe, an inverter G6 for inverting an output signal from the NAND gate G5, a PMOS pull-up transistor Q3 connected between a supply voltage source Vdd and a node N7, an NMOS pull-down transistor Q4 connected between the node N7 and a ground voltage source Vss, and an output terminal dout connected to the node N7. The PMOS pull-up transistor Q3 has its gate connected to an output terminal of the NAND gate G4 and the NMOS pull-down transistor Q4 has its gate connected to an output terminal of the inverter G6.
The operation of the conventional data output buffer circuit with the above-mentioned construction will hereinafter be described.
At the initial state, both the two data lines are precharged with low logic levels. Then, when the first and second read data signals rd and /rd are placed on the first and second read data lines, respectively, they are logically combined with the data output buffer enable signal oe by the NAND gate G4 and G5 and then applied to the gates of the PMOS pull-up transistor Q3 and NMOS pull-down transistor Q4. At this time, the PMOS pull-up transistor Q3 and the NMOS pull-down transistor Q4 are operated in response to voltage levels on nodes N4 and N6, respectively, to transfer data to the output terminal dout.
In the conventional data output buffer circuit of FIG. 2, both the two data lines rd and /rd are precharged with low logic levels at the initial state. Under this condition, the data output buffer enable signal oe is made active earlier than the read data signal to vary the output signal with a variation of the input signal. Therefore, the conventional data output buffer circuit can be operated at high speed. However, the conventional data output buffer circuit has a disadvantage in that it occupies a large area on the chip because of the use of two data lines.